I know the FVP(fast model) gives cycle count for NPU (90% accurate).
And it’s not cycle accurate or cycle approx.
My question is
does the FVP cycle count take into account data transfer latency/overhead/stalls from SRAM as well?
I’m using default U55 config.
Hi @slhskgsdlfjslg ,
Short answer: yes, it does.
FVP has a special module called timing adaptor (TA), it allows to emulate different memory bandwidth. TA could be controlled programmatically by setting certain registers.
TA allows to control AXI0 and AXI1 memory buses, for Ethos-U55 it would be SRAM and FLASH respectevely.
You can set the following parameters:
MAXR: Maximum number of pending read operations allowed.MAXW: Maximum number of pending write operations allowed.MAXRW: Maximum number of pending read and write operations allowed.RLATENCY: Minimum latency, in cycle counts, for a read operation. This is the duration between ARVALID and RVALID signals.WLATENCY: Minimum latency, in cycle counts, for a write operation. This is the duration between WVALID and WLAST, with BVALID being deasserted.PULSE_ON: The number of cycles where addresses are let through.PULSE_OFF: The number of cycles where addresses are blocked.BWCAP: Maximum number of 64-bit words transferred per pulse cycle. A pulse cycle is defined by PULSE_ON and PULSE_OFF.